Various tools have been developed for efficient design of a processor. As one of such tools, there is known a tool that generates a processor hardware configuration or processor software development tool according to design specification of a processor. Such a tool is hereinafter referred to as “processor design tool”. In conventional processor design tools, all information including instruction word length, operation code, and operand is defined by a designer. When defining one instruction, the designer defines the word length of the instruction and both type and number of operands used in the instruction.
Conventional processor design tools are disclosed in Non-Patent Citations 1 and 2 and Patent Citations 1 to 3. For example, a tool of Non-patent Citation 1 defines an instruction set of a processor to thereby generate a simulator of the processor. In the tool of Non-patent Citation 1, an instruction bit pattern is defined as follows.
CODING {Dest Src1 Src2 0b010000 0 b10000}
The portion between “{” and “}” represents a bit pattern. Dest, Src1, and Src2 each represent the register number. 0b010000 and 0b10000 following after Dest, Src1, and Src2 are each a binary digit representing an operation code of the instruction. In this manner, all information constituting the bit pattern of the instruction needs to be defined by the designer. The similar story goes for tools disclosed in Non-Patent Citation 2 and Patent Citations 1 and 2.
The instruction operation code is an instruction field for distinguishing one instruction from other instructions. In the case where the instruction set has been settled in advance, it is only necessary for designers to define the instruction operation code once in the beginning. However, when investigating what kind of an instruction is to be added to the instruction set, the designer needs to correct the instruction operation code several times.
If there is no need to define or correct the instruction operation code, the number of items to be defined by the designer is reduced. What value the operation code has is not important, but it is only necessary that the operation code be defined so as to make respective instructions distinguishable from each other. When a mechanism in which the instruction operation code can automatically be defined is achieved, the number of items to be defined by the designer can be reduced, leading to improvement in design efficiency.
Non-Patent Citation 1: S. Pees et al., “LISA-Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures”, 36th Design Automation Conference (DAC 99), June 1999, pp. 933-938
Non-Patent Citation 2: Andreas Hoffmann, et al., “A Survey on Modeling Issues Using the Machine Description Language Lisa,” Proceedings of ICASSP 2001, VOL. 2, pp. 1137-1140, May 7-11, 2001
Patent Citation 1: U.S. Pat. No. 6,477,683
Patent Citation 2: U.S. Pat. No. 6,862,563
Patent Citation 3: Jpn. PCT National Publication No. 2003-518280
Patent Citation 4: JP-A-2003-323463